High-accuracy Low-power ADC

high accuracy,low power,ADC



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    Zhejiang Jiaxing

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1.Chip Function Description

A124 is a high accuracy, low-power analog-to-digital conversion chip, a differential input channel, built-in temperature sensor and high accuracy oscillator.

The PGA of A124 is optional: 1, 2, 64, 128, the default is 128.

A124 The ADC data output rate in normal mode is optional: 10Hz, 40Hz, 640Hz, 1.28kHz, the default is 10Hz;

The MCU can communicate with the A124 through the 2-wire SPI interface SCLK, DRDY / DOUT, and configure it, such as channel selection, PGA selection, output rate selection, etc.


2.Main Functional Characteristics

Built-in crystal

Integrated temperature sensor

With power down function

2-wire SPI interface, the fastest rate is 1.1MHz

ADC Features:

24-bit no missing codes

Optional PGA magnification:1、2、64、128

One way 24-bit differential input without missing codes, ENOB is 20-bit (5V) \ 19.5-bit (3.3V) when PGA = 128

P-P  noise:PGA=128、10Hz:180nV;

INL < 0.0015%

Optional output rate:10Hz、40Hz、640Hz、1.28kHz

With internal short function


3.Chip Applications

Industrial process control

Electronic scale

Liquid / gas chemical analysis

Blood meter

Smart Converter

Portable devices

4.Basic Structural Functions


A124 is a high accuracy, low-power Sigma-Delta ADC chip with a built-in Sigma-Delta ADC, a differential input channel, and a temperature sensor. The ADC uses a two-order sigma delta modulator and uses an amplifier structure for low-noise instruments. To achieve PGA amplification, the magnification can be selected: 1, 2, 64, 128. When PGA = 128, the effective resolution can reach 20 bits (working at 5V).

A124 has a built-in RC oscillator, no external crystal is required.

A124 can be configured through DRDY / DOUT and SCLK in multiple functional modes, such as temperature detection, PGA selection, ADC data output rate selection, etc.

A124 has Power down mode.

Power DOWN 


5.POR&power down

When the chip is powered on, the built-in power-on reset circuit will generate a reset signal to reset the chip automatically.

When SCLK changes from low level to high level and stays at high level for more than 100µs, A124 enters PowerDwon mode, and the power consumption is lower than 0.1μA. When SCLK returns to low level again, the chip will enter normal working state again.

When the system enters the normal working mode from Power down, all functions are configured to the state before Power Down, and no function configuration is required.



6.Low Noise PGA Amplifier


A124 provides a low-noise and low-drift PGA differential output connection of amplifier and bridge sensor, its basic structure diagram is shown in the following figure. Front anti-EMI filter circuit R = 450Ω, C = 18pF to realize 20M high frequency filtering. The low-noise PGA amplifier realizes 64-fold amplification through RF1, R1, and RF2, and forms 64 and 128 PGA amplification with the post-stage switched capacitor PGA.It configures different PGAs (1, 2, 64, 128)through pga_sel [1: 0]. When PGA = 1, 2, the 64 times low noise PGA amplifier will be turned off to save power. When using a low-noise PGA amplifier, the input range is between GND + 0.75V and VDD-0.75V. Exceeding this range will cause actual performance degradation.Connect a built-in 45pF capacitor at the CAP port to form a low-pass filter with the built-in 2k resistor RINT, which is used as a high-frequency filter for the output signal of the low-noise PGA amplifier, and the low-pass filter can also be used as an anti-aliasing filter for the ADC Device.


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